Journal of Zhejiang University SCIENCE
(ISSN 1009-3095, Monthly)
2003   Vol. 4   No. 3   p.281-286

Noise and linearity optimization methods for a 1.9GHz low noise amplifier

GUO Wei(¹ùΪ)(Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China)
HUANG Da-quan(»Æ´ïÚ¹)(Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China)

Abstract:Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. The 1.9GHz Complementary Metal-Oxide-Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.
Keywords:RFIC, CMOS LNA, NF, noise, IP3, linearity

CLC Number:TN722.3 Document ID:A

Author Resume:GUO Wei,E-mail: alohagw@isee.zju.edu.cn

References:

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Manuscript Received:2002 May 3

Manuscript Revised:2002 July 5

Published:2003 June 1